L.M. Struck, J.A. Small, E.B. Steel, D.S. Simons, P.H. Chi, A.F. Myers, E.S. Windsor, and J.R. Whetstone

Objectives: To solve problems in deep submicrometer CMOS process technology by utilizing multidisciplinary diagnostic tools.

Problem: A collaborative effort has been established between scientists in CSTL and the Microelectronics Laboratory at M.I.T. Lincoln Laboratory to solve problems in deep submicrometer CMOS process technology by utilizing multidisciplinary diagnostic tools and scientific expertise available in the Surface and Microanalysis Science Division (837) and the Process Measurements Division (836). The M.I.T. Lincoln Laboratory group fabricates deep submicrometer silicon-on-insulator (SOI) CMOS devices with the goal of developing advanced processing technology. While Lincoln Labs has state-of-the-art fabrication facilities and expertise in device fabrication, they do not have state-of-the-art analytical tools and the necessary expertise in these analytical areas. NIST participation allows more direct identification of problems encountered by Lincoln Labs in their process development efforts.

Approach: The approach was to characterize actual devices and blanket films of the material of interest that were processed by the same procedure as in the device. The analytical techniques that we have used to investigate various properties of the devices or thin films have included scanning electron microscopy (SEM), Secondary Ion Mass Spectrometry (SIMS) depth-profiling measurements, and Transmission Electron Microscopy (TEM).
 

Results and Future Plans: The SEM image in Figure 1 is the cross section image of an individual transistor that was obtained using a Field Emission SEM. The contrast for this image was improved by etching the device in dilute HF. The etch rate is different for different materials and even within the same material, areas having more defects will etch preferentially. The image shows layers identified as the (a) silicon wafer, (b) buried silicon oxide, (c) cobalt silicide layer to the right, (d) top layer of silicon oxide, (e) silicon channel to the left, (f) polysilicon gate, and (g) spacer oxide. Additionally, a void (h) was consistently seen between the cobalt silicide and the silicon channel in these devices. The poor performance of these devices may well be due to these voids or their precursors. Insights into other important aspects of the processing parameters have also been gained by characterizing the quality of areas such as the top layer of silicon oxide, the polysilicon gate, and the spacer oxide. In another series of experiments, degradation in device characteristics after thermal treatment was initially thought to be due to dopant redistribution. Three sets of n- and p-doped silicon wafers with CoSi2 films were analyzed by SIMS to determine dopant depth profiles. The SIMS analyses concluded that there is no evidence of significant dopant redistribution as a function of heat treatment. We are currently investigating the effects of several processing parameters and steps (such as the use of a TiN capping layer) on the quality of titanium silicide film with high resolution transmission electron microscopy, selected area electron diffraction, scanning TEM, energy dispersive x-ray spectroscopy, and electron energy loss spectroscopy.

Figure 1. Field Emission SEM micrograph of a cleaved-etched cross section of a transistor.

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